1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing integrated circuits, and, more particularly, to the formation of device features on the basis of lithography techniques requiring sensitive focus parameters.
2. Description of the Related Art
Typically, the fabrication of modern integrated circuits includes a complex process flow, in which a large number of individual processes are performed, such as deposition, implantation, etching, lithography and the like. For example, a typical process sequence frequently encountered may involve the deposition of conductive, semiconductive or insulating material layers on an appropriate substrate. After deposition of the corresponding layer, device features may be formed in the material layer by patterning the corresponding layer on the basis of photolithography and etch techniques, thereby creating a certain topography by the resulting features, such as trenches, vias, lines and the like, which are formed from the underlying material layer. The resulting surface topography may also affect further manufacturing processes, such as the deposition and patterning of subsequent layers. Since sophisticated integrated circuits are typically comprised of a plurality of stacked material layers, each of which may bear a specified spatial relationship to underlying and overlying layers, it has become standard practice to periodically planarize the surface of the substrate to provide well-defined conditions for deposition and patterning of subsequent material layers. This holds especially true for so-called metallization layers in which metal interconnect structures are formed to electrically connect the individual device features, such as transistors, capacitors, resistors and the like, to establish the functionality required by the circuit design.
Recently, the so-called damascene or inlaid technique has become a preferred method in forming metallization layers, wherein a dielectric layer is deposited and patterned to include trenches and vias that are subsequently filled with an appropriate metal, such as copper, copper alloys and the like. In this manufacturing regime, the previously formed trenches and/or vias have to be filled such that the various openings, which may have different sizes, may be reliably filled, thereby requiring the deposition of a certain amount of excess material. The excess metal is then removed and the resulting surface is planarized by performing a planarization process which may typically comprise a chemical mechanical polishing (CMP) process. Chemical mechanical polishing (CMP) has proven to be a reliable technique to remove the excess metal and planarize the resulting surface to leave behind metal trenches and vias that are electrically insulated from each other as required by the corresponding circuit layout. Chemical mechanical polishing typically requires the substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other by individually moving the polishing head and the polishing pad. Typically, the head and pad are moved against each other while controlling the relative motion to achieve as uniform a material removal as possible.
However, the removal rate may not only depend on the characteristics of the chemical and mechanical adjustments of the polishing process but also on the type of materials to be polished and the local pattern geometry. For instance, at a polishing state where the major portion of the metal has already been removed, the dielectric material and metal, such as copper, barrier material and the like, may be treated concurrently with different removal rates, thereby resulting in a certain degree of non-uniformity, wherein a varying degree of metal coverage of the currently polished surface, due to a difference in pattern density with respect to the metal regions, may also contribute to corresponding overall non-uniform planarity. For example, the presence of a plurality of closely spaced metal lines may result in a higher total removal rate for the dielectric material and the metal compared to areas including isolated lines. The resulting different non-uniformity of the surface topography may, however, affect subsequent processes, such as the deposition of dielectric materials and the patterning thereof on the basis of sophisticated lithography techniques, due to the very restricted process window when highly scaled devices are considered, as will be explained in more detail with reference to FIGS. 1a-1c. 
FIGS. 1a-1c schematically illustrate cross-sectional views of a semiconductor device 100 at various stages during the fabricating of a metallization layer according to a typical damascene process sequence.
In FIG. 1a, the semiconductor device 100 comprises a substrate 101 including circuit features and any other components related thereto, which, for convenience, are not shown in FIG. 1a. Furthermore, a dielectric layer 102 may be provided above the substrate 101, and above any circuit elements formed therein and thereon, which may represent the dielectric material of a respective metallization layer of the device 100. The dielectric layer 102 may be comprised of any appropriate material, such as silicon dioxide, silicon nitride and the like, wherein, in sophisticated applications, the dielectric layer 102 may at least be partially comprised of a low-k dielectric material having a relative permittivity of approximately 3.0 and significantly less. Furthermore, in and above the dielectric layer 102 are defined device areas 110A, 110B in which different structural characteristics, such as pattern density and the like, may result in respective non-uniformities of the resulting surface topography. For instance, in the area 110A, a plurality of closely spaced metal-filled trenches 103 may be provided, while the area 110B may be characterized by a significantly reduced metal density, for instance by including an isolated metal trench 104. It should be appreciated that the areas 110A, 110B are illustrative examples of different structural characteristics with respect to the effective “averaged” metal contents in respective device areas. Furthermore, it should be appreciated that the device areas 110A, 110B may not necessarily be defined by well-defined boundaries but may be substantially determined by the corresponding “global” or “averaged” effect during certain manufacturing processes, such as a CMP process, which will be described later on in more detail. The metal-filled trenches 103, 104 may comprise highly conductive metal materials, such as copper, copper alloys and the like, which may typically be provided in combination with respective barrier materials (not shown) in order to reduce out-diffusion of copper material, enhance the adhesion thereof to the neighboring dielectric material and reduce any interaction of reactive components with the highly sensitive copper material.
Typically, the semiconductor device 100 as shown in FIG. 1a may be formed on the following process techniques. After the completion of any circuit elements including respective contact portions and the like, the dielectric layer 102 may be formed on the basis of well-established recipes, which may include the deposition of an etch stop material (not shown) followed by the application of an appropriate dielectric material, such as a low-k dielectric material or a combination of a silicon dioxide-based dielectric material in combination with other low-k dielectric materials, depending on the device requirement. Next, sophisticated lithography processes may be performed in order to form appropriate openings in the dielectric layer 102, wherein sophisticated lithography techniques may be used, as will be described later on with reference to FIG. 1b. Thereafter, the resulting openings, such as trenches and the like, may be filled with an appropriate conductive material, wherein typically respective barrier materials may be deposited, for instance on the basis of chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like. Subsequently, after providing appropriate seed materials, such as copper and the like, the copper-based material may be deposited on the basis of a wet chemical deposition process requiring highly sophisticated process regimes to fill the respective trenches from bottom to top in a substantially void-free manner. Furthermore, in order to reliably fill the respective trenches, which may have different lateral sizes, depth and the like, a certain amount of excess material may also be formed on horizontal surface portions of the device 100, wherein the resulting surface topography may depend significantly on the local deposition conditions, which, in turn, may be determined, among others, by the different pattern densities in the respective areas 110A, 110B. After the deposition process, the corresponding excess material may be removed, wherein usually a CMP process may be applied, at least at a final phase. During the removal of the copper material, the seed layer and the barrier materials, highly complex CMP process conditions may occur during the final phase of the CMP process, thereby resulting in respective surface non-uniformities, that is, in the various device areas 110A, 110B, different height levels may be created locally, as is, for instance, indicated by the dashed line 111, which may represent enhanced material removal of the dielectric material and the metal in the trenches 103 compared to the situation in the area 110B. It should further be appreciated that the respective surface topography of the area 110A may further comprise a certain “fine structure” since the material erosion in the respective trenches 103 compared to the neighboring dielectric areas may also be different, which is however not shown in FIG. 1a. Consequently, although a generally substantially flat surface topography may be provided, nevertheless a certain degree of non-planarity with respect to the specified device areas 110A, 110B may have been created, for instance by CMP, thereby providing a difference in height levels and thus a certain amount of non-planarity which may vary depending on device-specific characteristics, such as pattern density and the like.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. Here, a further dielectric layer 103 may be provided, followed by an anti-reflective coating (ARC) 104 and a resist layer 105 in order to prepare the device 100 for a further sophisticated lithography process in order to pattern the dielectric layer 103 for receiving via openings and/or trenches, depending on the process requirements. As previously explained, one essential process in the manufacturing of semiconductor devices is the lithography process, since exposure processes at the various device levels represent the major part of the overall production costs while also providing the potential for compensating for across-substrate non-uniformities and also rectifying exposure-specific errors prior to permanently transferring such exposure-specific errors into the semiconductor structure, such as the dielectric layer 103. It is thus of great importance to provide process conditions for reliably imaging the respective device features having the minimum lateral dimensions of the circuit design of the respective process layer under consideration into the resist material 105. The resolution of the corresponding imaging process is substantially determined by the numerical aperture of the imaging system, the exposure wavelength and the depth of focus. For obtaining an increased resolution, typically the exposure wavelength may be reduced, which results, for a fixed numerical aperture, in a reduced depth of focus. For instance, with ever decreasing exposure wavelengths, which may presently be at approximately 190 nm for critical lithography processes also used in the metallization level, the requirements with respect to appropriately focusing each exposure field are becoming more and more stringent. In an exposure process, therefore, highly complex and automated procedures are performed in order to appropriately align and focus the substrate to be exposed. The alignment and focusing procedure is usually performed individually for each exposure field in a step and scan system and may thus require different alignment and focusing values of the respective parameters. For example, in the presence of non-uniformities of the resulting surface topography, for instance the respective non-uniformity 111 in the areas 110A, 110B, which may represent respective areas within a specific die region and which may therefore be contained in the same exposure field, the respective exposure process may result in slightly defocused latent images in some of these areas, depending on the respective non-uniformities. Thus, during a lithography process 106, the difference in planarity in the regions 110A, 110B, as indicated by 111, may cause respective non-uniformities of the imaging process and subsequently respective non-uniformities during the patterning of the dielectric layer 103. Hence, respective patterning errors and even missing patterns may occur due to the CMP-induced non-uniformities 111.
FIG. 1c schematically illustrates a cross-sectional view of the device 100 in an advanced manufacturing stage, wherein respective via openings 107 may be formed above the area 110A, and a corresponding opening 108 may be formed above the area 110B. As illustrated, the difference in the surface planarity may result in respective patterning errors or even missing features, wherein it may be assumed that the respective focus conditions may not have been appropriate for the area 110A. In this case, the respective resist features formed from the resist layer 105 on the basis of the exposure process 106 may result in corresponding pattern transfer errors during the subsequent anisotropic etch process, finally resulting in faulty interconnect structures.
Thus, although the critical dimensions of the respective device level, such as the level formed on the basis of the exposure process 106, may be monitored and controlled on the basis of appropriately designed CD (critical dimension) measurement structures during respective metrology strategies, the corresponding patterning errors, such as the faulty openings 107, may not be efficiently detected by conventional CD monitoring techniques but may require sophisticated electrical tests, thereby additionally increasing cycle time, increasing defect rate caused by the additional electrical tests and the like. Furthermore, respective electrical measurement data of focus related patterning errors may be available after permanently transferring the respective patterns into the respective device level, thereby producing respective faulty devices in exposure fields processed on the basis of inappropriate focusing parameters.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.